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cha5050 - qdg rohs compliant ref. : dscha5050qdg1216 - 04 aug 11 1 / 14 specifications subject to change without notice united monolithic semiconductors s.a.s. route dpartementale 128 - bp46 - 91401 orsay cedex france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 17 - 24ghz medium power amplifier gaas monolithic microwave ic in smd leadless package description the cha5050 - qdg is a m edium power amplifier four stages monolithic circuit . it is designed for a wide range of applications, from military to commercial communication systems. the circuit is manufa ctured with a phemt process, 0.1 5m gate length, via holes through the substrate, air bridges and electron beam gate lithography. it is supplied in rohs compliant smd package. main features main electrical characteristics tamb. = + 25c , vd = vd1 = vd2 = vd3 = vd4 = 6.0v , id = 230ma symbol parameter min typ max unit freq frequency range 17 24 ghz gain linear gain 22 db p 1db output power @ 1db compression 25 db m psat saturated output power 26 dbm oip3 output ip3 30 dbm ums a5050 yyww ? ? ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg ums a3667a yywwg ums a3667a yywwg ums a3688a yywwg
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 2 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 electrical characteristics tamb. = + 25c , vd = vd1 = vd2 = vd3 = vd4 = 6.0v symbol parameter min typ max unit fop operating frequency range 17 24 ghz g small signal gain 22 db p 1db output power @ 1db compression 25 db m psat saturated output power 26 dbm oip3 output ip3 30 dbm rlin input return loss - 7 db rlout output return loss - 9 db v g dc gate voltage - 0.5 v id total drain current 230 ma these values are representative of onboard measurements as defined on the drawing in paragraph "evaluation mother board". absolute maximum ratings (1) tamb.= + 2 5c symbol parameter values unit vd drain bias voltage 6 .5 v id drain bias current 300 ma vg gate bias voltage - 2 to +0.4 v pin maximum peak input power overdrive (2) + 8 dbm tj junction temperature 175 c ta operating temperature range - 40 to +85 c tstg storage temperature range - 55 to +15 0 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) duration < 1s. typical bias conditions tamb.= + 25c symbol pad n o parameter values unit vd4, vd3, vd2 , vd 1 7, 9, 10, 12 drain voltage 6.0 v id 7, 9, 10, 12 drain current controlled with vg 230 ma vg 22 gate voltage - 0.5 v
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 3 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 device thermal performances all the figures given in this section are obtained assuming that the qfn device is cooled down only by conduction through the package thermal pad (no convection mode considered). the temperature is monitored at the package back - side interface (tcase) as shown below. the system maximum temperature must be adjusted in order to guarantee that tcase remains below than the maximum value specified in the next table. so, the system pcb must be designed to comply with this requireme nt. a derating must be applied on the dissipated power if the tcase temperature can not be maintained below than the maximum temperature specified (see the curve pdiss. max) in order to guarantee the nominal device life time (mttf). recommended max. junction temperature (tj max) : 141 c junction temperature absolute maximum rating : 175 c max. continuous dissipated power (pdiss. max.) : 1.4 w => pdiss. max. derating above tcase (1) = 85 c : 24 mw/c junction-case thermal resistance (rth j-c) (2) : <40 c/w minimum tcase operating temperature (3) : -40 c maximum tcase operating temperature (3) : 85 c minimum storage temperature : -55 c maximum storage temperature : 150 c (1) derating at junctio n temperature co nstant = tj max. (2) rth j-c is calculated fo r a wo rst case co nsidering the ho t t e s t junc t io n o f the m m ic and all the devices biased. (3) tcase=p ackage back side temperature measured under the die-attach-pad (see the drawing belo w). 6.1 device thermal specification : cha5050-qdg 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 - 50 - 25 0 25 50 75 100 125 150 175 pdiss. max. @tj cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 4 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical package sij parameters tamb.= +25c , vd = vd1 = vd2 = vd3 = vd4 = 6.0v , id = 230ma freq (ghz) s11 (db) phs11 () s12 (db) phs12 () s21 (db) phs21 () s22 (db) phs22 () 2 - 0.15 - 43.46 - 79.12 82.91 - 93.09 164.10 - 0.10 - 42.52 3 - 0.26 - 65.21 - 84.47 139.40 - 79.29 25.76 - 0.17 - 64.72 4 - 0.34 - 86.45 - 75.82 - 124.90 - 76.78 - 141.20 - 0.19 - 88.18 5 - 0.67 - 109.30 - 71.70 - 131.10 - 62.69 - 122.80 - 0.41 - 110.60 6 - 0.92 - 130.50 - 69.28 165.70 - 51.22 169.10 - 0.83 - 138.00 7 - 1.42 - 151.70 - 67.06 88.13 - 39.69 100.50 - 1.61 - 165.60 8 - 1.90 - 175.20 - 62.98 87.70 - 28.67 26.75 - 3.05 167.40 9 - 2.89 154.90 - 65.44 44.97 - 19.03 - 56.92 - 5.89 149.10 10 - 4.10 131.00 - 66.59 - 63.19 - 12.25 - 138.70 - 9.39 130.70 11 - 6.29 110.20 - 64.11 - 74.28 - 6.13 149.80 - 19.41 118.30 12 - 10.06 82.48 - 76.01 145.90 - 1.12 78.12 - 14.19 - 153.90 13 - 18.87 53.88 - 58.93 114.50 3.47 15.51 - 9.91 - 170.10 14 - 21.88 - 162.80 - 54.27 105.60 9.91 - 44.55 - 7.87 - 179.50 15 - 13.42 158.20 - 52.66 87.41 16.80 - 118.70 - 6.51 158.40 16 - 16.95 115.40 - 51.19 57.99 21.93 144.40 - 6.85 128.00 17 - 15.06 177.90 - 49.55 21.75 22.82 55.31 - 9.02 102.40 18 - 9.61 150.10 - 58.59 14.67 22.84 - 23.65 - 12.37 68.24 19 - 7.45 124.80 - 58.33 7.12 22.45 - 95.31 - 19.02 40.89 20 - 6.66 100.90 - 58.49 6.88 21.84 - 158.90 - 22.77 31.90 21 - 6.47 79.07 - 55.71 49.41 21.94 140.30 - 21.18 11.18 22 - 6.65 56.92 - 64.74 17.23 22.25 79.89 - 19.53 - 14.93 23 - 7.77 38.68 - 52.31 77.06 22.66 18.99 - 18.83 - 45.54 24 - 8.73 19.38 - 49.00 47.85 23.47 - 44.50 - 19.50 - 58.31 25 - 11.58 12.05 - 46.33 12.35 24.08 - 115.30 - 28.26 - 19.30 26 - 9.64 17.46 - 48.81 - 7.73 23.83 170.80 - 13.90 14.74 27 - 6.74 - 1.09 - 48.77 - 9.68 22.20 94.00 - 8.81 - 13.81 28 - 4.45 - 25.01 - 45.91 13.83 19.73 19.57 - 6.77 - 37.10 29 - 2.70 - 54.65 - 43.31 0.89 16.01 - 53.66 - 5.28 - 62.66 30 - 1.71 - 84.20 - 40.58 - 23.57 11.45 - 120.30 - 4.57 - 92.53 31 - 1.09 - 110.70 - 38.13 - 40.14 6.53 176.90 - 4.14 - 127.00 32 - 0.43 - 135.10 - 36.52 - 79.36 1.40 116.70 - 3.81 - 165.60 33 0.07 - 157.60 - 38.59 - 141.90 - 4.67 58.50 - 3.30 158.70 34 0.48 - 178.40 - 55.80 - 143.50 - 11.29 3.64 - 2.54 128.80 35 0.42 162.70 - 54.29 - 123.80 - 19.26 - 45.30 - 1.92 104.80 36 0.10 147.10 - 50.38 - 59.24 - 27.82 - 83.84 - 1.32 86.13 37 - 0.19 133.00 - 48.15 - 44.33 - 37.07 - 93.46 - 0.94 70.42 38 - 0.40 121.10 - 44.07 - 51.65 - 40.71 - 72.72 - 0.81 57.16 39 - 0.50 108.50 - 39.58 - 75.49 - 38.32 - 78.30 - 0.71 44.64 40 - 0.47 95.99 - 38.86 - 102.30 - 38.42 - 95.95 - 0.73 30.49
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 5 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical board measurements tamb.= +25c, vd = +6.0v, vg = - 0.5v, id = 230ma if no specific mention, the following values are representative of on board measurements (i n qfn access planes) as defined on the paragraph evaluation mother board. linear gain & return loss versus frequency at room temperature linear gain versus frequency & temperature ( - 0.016db/c and per stage) -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 15 16 17 18 19 20 21 22 23 24 25 26 27 28 frequency (ghz) gain & return loss (db) s11 s22 s21 16 18 20 22 24 26 28 30 17 18 19 20 21 22 23 24 25 26 frequency (ghz) linear gain (db) -40 c +25 c +85 c
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 6 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical board measurements tamb.= +25c, vd = +6.0v, vg = - 0.5v, id = 230ma output power at 1db compression versus frequency gain & output power versus input power & frequency 20 21 22 23 24 25 26 27 28 29 30 17 18 19 20 21 22 23 24 25 26 frequency (ghz) ouput power at 1 db compression (dbm) 0 5 10 15 20 25 30 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 pin (dbm) gain (db) & output power (dbm) 17 ghz 19 ghz 21 ghz 24 ghz
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 7 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical board measurements vd = +6.0v, vg = - 0.5v, id = 230ma output ip3 versus frequency & temperature drain current versus input power & temperature @ 20ghz 25 26 27 28 29 30 31 32 33 34 35 16 17 18 19 20 21 22 23 24 25 0ip3 (dbm) frequency (ghz) +25 c - 40 c +85 c 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 - 20 - 18 - 16 - 14 - 12 - 10 - 8 - 6 - 4 - 2 0 2 4 6 8 id (a) pin (dbm) - 40 c +25 c +85 c
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 8 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical board measurements tamb.= +25c, vd = +6.0v, vg = - 0.5v, id = 230ma c/i3 versus pout dcl & frequency at ambient temperature c/i3 versus pout dcl at 1 7 ghz c/i3 versus pout dcl at 19 ghz c/i3 versus pout dcl at 21 ghz c/i3 versus pout dcl at 24 ghz 10 15 20 25 30 35 40 45 50 55 7 9 11 13 15 17 19 21 23 25 c/i3 (db) pout dcl (dbm) 17 ghz 19 ghz 21 ghz 24 ghz 10 15 20 25 30 35 40 45 50 55 7 9 11 13 15 17 19 21 23 25 c/i3 (db) pout dcl (dbm) - 40 c +25 c +85 c 10 15 20 25 30 35 40 45 50 55 7 9 11 13 15 17 19 21 23 25 c/i3 (db) pout dcl (dbm) - 40 c +25 c +85 c 10 15 20 25 30 35 40 45 50 55 7 9 11 13 15 17 19 21 23 25 c/i3 (db) pout dcl (dbm) - 40 c +25 c +85 c 10 15 20 25 30 35 40 45 50 55 7 9 11 13 15 17 19 21 23 25 c/i3 (db) pout dcl (dbm) - 40 c +25 c +85 c
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 9 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 package outline (1) matt tin, lead free (green) 1 - nc 9 - vd3 17 - gnd (2) units : mm 2 - gnd (2) 10 - vd2 18 - nc from the standard : jedec mo - 220 3 - gnd (2) 11 - gnd (2) 19 - nc (vggd) 4 - rf out 12 - vd1 20 - nc 25 - gnd 5 - gnd (2) 13 - gnd (2) 21 - nc 6 - gnd (2) 14 - gnd (2) 22 - vg 7 - vd4 15 - rf in 23 - nc 8 - gnd (2) 16 - gnd (2) 24 - nc (1) the package outline drawing included to this data - sheet is given for indication. refer to the application note an0017 ( http://www.ums - gaas.com ) for exact package dimensions. (2) it is strongly recommended to ground all pins marked gnd through the pcb board.
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 10 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 definition of the sij reference planes the reference planes used for sij measurements given above are symmetrical from the symmetrical axis of the package (see drawing beside). the input and output reference planes are located at 3.18mm offset (input wise and output wise respectively) from this axis. then, the given sij parame ters incorporate the land pattern of the evaluation motherboard recommended in paragraph "evaluation mother board". 3.18 3.18
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 11 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 evaluation mother board compatible with the proposed footprint. based on typically ro4003 / 8mils or equivalent. using a micro - strip to coplanar transition to access the package. recommended for the implementation of this prod uct on a module board. decoupling capacitors of 10nf ? 10% , 100pf ? 5% and 1f ? 10% are recommended for all dc access . see application no te an0017 for details.
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 12 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 notes
17 - 24ghz medium power amplifier cha5050 - qdg ref. : dscha5050qdg1216 - 04 aug 11 13 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 dc schematic i d =230ma
cha5050 - qdg 17 - 24ghz medium power amplifier ref. : dscha5050qdg1216 - 04 aug 11 14 / 14 specifications subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 recommended package footprint refer to the application note an0017 available at http://www.ums - gaas.com for package foot print recommendations. smd mounting procedure for the mounting process standard techniques involving solder paste and a suitable reflow process can be used. for further details, see application note an0017. recommended environmental management refer to the application note an0019 available at http://www.ums - gaas.com for environmental data on ums package products. recommended esd management refer to the application note an0020 available at http://www.ums - gaas.com for esd sensitivity and handling recommendations for the ums package products. ordering information qfn 4x4 rohs compliant package: cha5050 - qdg /xy stick: xy = 20 tape & reel: xy = 21 information furnished is believed to be accurate and reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in thi s publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or systems without express written approval from united monolithic semiconductors s.a.s.

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